PPAPlace: Differentiable cross-stage objectives for chip placement optimization
Read the original at arxiv.org→arXiv:2608.13790v1 Announce Type: new Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the...
Original headline: "PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization"
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- Aug 17, 04:00 UTC arXiv cs.LG lead source PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization